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riscv-zvbb

1.0.0Readiness: RL1Packaged

by extensilica

Vector crypto bit-manipulation extension

Conflicts with 7 extension(s)
Show encoding conflict details

riscv-zvbc INFO

  • SHARED_MAJOR_OPCODE: opcode 0x57 — shared major opcode; not a conflict by itself. A true conflict requires overlapping full decode mask/match patterns, including any fixed register/immediate field constraints.

riscv-zvkg INFO

  • SHARED_MAJOR_OPCODE: opcode 0x57 — shared major opcode; not a conflict by itself. A true conflict requires overlapping full decode mask/match patterns, including any fixed register/immediate field constraints.

riscv-zvkned INFO

  • SHARED_MAJOR_OPCODE: opcode 0x57 — shared major opcode; not a conflict by itself. A true conflict requires overlapping full decode mask/match patterns, including any fixed register/immediate field constraints.

riscv-zvknha INFO

  • SHARED_MAJOR_OPCODE: opcode 0x57 — shared major opcode; not a conflict by itself. A true conflict requires overlapping full decode mask/match patterns, including any fixed register/immediate field constraints.

riscv-zvknhb INFO

  • SHARED_MAJOR_OPCODE: opcode 0x57 — shared major opcode; not a conflict by itself. A true conflict requires overlapping full decode mask/match patterns, including any fixed register/immediate field constraints.

riscv-zvksed INFO

  • SHARED_MAJOR_OPCODE: opcode 0x57 — shared major opcode; not a conflict by itself. A true conflict requires overlapping full decode mask/match patterns, including any fixed register/immediate field constraints.

riscv-zvksh INFO

  • SHARED_MAJOR_OPCODE: opcode 0x57 — shared major opcode; not a conflict by itself. A true conflict requires overlapping full decode mask/match patterns, including any fixed register/immediate field constraints.

Pre-silicon bridge: this package is meant to be evaluable before RTL/FPGA/ASIC decisions.

Readiness & capabilities

Readiness: RL1Packaged

Runnable (entry declared)
Testable (testEntry declared)
Repro: bundled
Repro: resolved
Repro: host-dependent
Toolchain: bundled
Toolchain: external
Sim: Spike
Emu: QEMU
RTL
FPGA
Tests

README

Vector crypto bit-manipulation extension

Version History

VersionPublishedStatus
1.0.0latest

Initial catalog-seed scaffold for riscv-zvbb (10 base mnemonics, 16 concrete encodings), derived from upstream 9cb9087.

xsil install [email protected]
May 12, 2026active

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