riscv-zvknhb

1.0.0.xsil package

by extensilica

Vector SHA-256 + SHA-512 instruction extension

No confirmed encoding conflictsShares encoding space with 7 extension(s)

Show encoding relation details

riscv-zvbb INFO

SHARED_MAJOR_OPCODE: opcode 0x57 — shared major opcode; not a conflict by itself. A true conflict requires overlapping full decode mask/match patterns, including any fixed register/immediate field constraints.

riscv-zvbc INFO

SHARED_MAJOR_OPCODE: opcode 0x57 — shared major opcode; not a conflict by itself. A true conflict requires overlapping full decode mask/match patterns, including any fixed register/immediate field constraints.

riscv-zvkg INFO

SHARED_MAJOR_OPCODE: opcode 0x57 — shared major opcode; not a conflict by itself. A true conflict requires overlapping full decode mask/match patterns, including any fixed register/immediate field constraints.

riscv-zvkned INFO

SHARED_MAJOR_OPCODE: opcode 0x57 — shared major opcode; not a conflict by itself. A true conflict requires overlapping full decode mask/match patterns, including any fixed register/immediate field constraints.

riscv-zvknha INFO

OPCODE_SHARED: vsha2ms.vv — same instruction in both extensions by spec (encoding details not yet imported)

riscv-zvksed INFO

SHARED_MAJOR_OPCODE: opcode 0x57 — shared major opcode; not a conflict by itself. A true conflict requires overlapping full decode mask/match patterns, including any fixed register/immediate field constraints.

riscv-zvksh INFO

SHARED_MAJOR_OPCODE: opcode 0x57 — shared major opcode; not a conflict by itself. A true conflict requires overlapping full decode mask/match patterns, including any fixed register/immediate field constraints.

This versioned archive records the Extension's encoding, dependencies, provenance, documentation, and any simulator, toolchain, RTL, test, or hardware support declared by its maintainer.

Install package

xsil install riscv-zvknhb

Details

Published

May 14, 2026

Latest

1.0.0

Standard

Ratified

RISC-V International

Provenance

Seeded · unverified

Auto-published from upstream by the ExtenSilica catalog-seed agent. The original maintainer has not (yet) claimed authorship.

ISA

RV64GV_ZVKNHB

Cite

CFF and BibTeX for papers and Zenodo (v1.0.0).

CFF

cff-version: 1.2.0
type: software
title: riscv-zvknhb
version: 1.0.0
authors:
  - name: extensilica
abstract: Vector SHA-256 + SHA-512 instruction extension
message: "If you use this software, please cite it using the metadata from this file."
repository-code: https://github.com/riscv/riscv-crypto
url: https://extensilica.com/package/riscv-zvknhb
date-released: 2026-05-14
identifiers:
  - type: url
    value: https://extensilica.com/package/riscv-zvknhb
  - type: url
    value: https://github.com/riscv/riscv-crypto

BibTeX

@software{riscv_zvknhb_1_0_0,
  title = {riscv-zvknhb},
  author = {extensilica},
  year = {2026},
  version = {1.0.0},
  url = {https://extensilica.com/package/riscv-zvknhb},
  repository = {https://github.com/riscv/riscv-crypto},
}

Downloads

7 days

30 days

Maintainers

extensilica

Links

Repository

Package metadata

Metadata is published by the package maintainer. Inspect the archive, upstream sources, and checksums before depending on declared support.

Required ISA: RV64GV_ZVKNHB
Declared support: spike
Toolchain: riscv64-unknown-elf · v14.2.0 (external)
Capabilities: ISAToolchain: externalSim: SpikeTestsRepro: host-dependententrytestEntry
Resolution: host-dependent
Archive checksum: sha256:bfc5e78b091ecabb3ceefbc88c7adadb9231e128d8043c09df66fe3ae94ebe69
Payload checksum: sha256:795ca4c9d27e7e592eeb9e181cfde93d7d4f6c74b6a073c15a0b83b15d2cefe3

Support metadata

{
  "spike": {
    "config": "sim/spike.yaml",
    "isa": "rv64gv_zvknhb",
    "mem": "256m",
    "priv": "msu",
    "status": "skeleton"
  }
}

Dependencies

{
  "tools": []
}

README

Vector SHA-256 + SHA-512 instruction extension

Version History

Version	Published	Size	Downloads	Status
1.0.0latest `xsil install [email protected]`	May 14, 2026	4.4 KB	1	active

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07-1307-2007-2708-0308-1008-11

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1.0.0

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