@extensilica

Mojo-V privacy-oriented secret computation extension (UMich research)

Basic bit-manipulation crypto helper extension

SHA-256 / SHA-512 hash instruction subset

Entropy source / crypto CSR support

Qualcomm Xqci arithmetic/control extension family

Crossbar / permutation helper extension for crypto

SM3 hash instruction subset

AES encryption instruction subset

T-Head XTheadFMemIdx floating-point indexed memory operations

SiFive vector quantized MAC quad/quad family

SiFive cease / stop instruction extension

Vector crypto bit-manipulation extension

AES decryption instruction subset

Vector carry-less multiply extension

Archived ExtenSilica portability experiment preserved for historical reference. It is not part of the public extension catalog.

Qualcomm Xqci interrupt/integer family

Data-independent execution latency subset

XMAC → PicoRV32 PCPI port evidence: generated Verilog adapter + differential test report.

Carry-less multiply extension for cryptographic workloads

SiFive vector quantized MAC dot/odd family

SM4 block cipher instruction subset

Vector ShangMi + GCM (Zvks + Zvkg)

Qualcomm Xqci compressed / memory family

Vector SHA-256 + SHA-512 instruction extension

Qualcomm Xqci bit/integer instruction family

SiFive matrix / memory-related vendor family

Qualcomm Xqci compressed / load-immediate style family

Vector crypto bit-manipulation subset (subset of Zvbb)

SiFive VCIX coprocessor opcode / intrinsic family

Vector ShangMi + carry-less multiply (Zvks + Zvbc)

Standard scalar crypto umbrella (Zkn + Zkr + Zkt)

Qualcomm Xqci loop/control family

SiFive vector fixed-point narrowing / clipping family

Vector NIST + GCM (Zvkn + Zvkg)

Vector NIST crypto suite (Zvkned + Zvknhb + Zvkb + Zvkt)

ShangMi scalar crypto suite (Zbkb + Zbkc + Zbkx + Zksed + Zksh)

Vector crypto timing / data-independent execution subset

Qualcomm Xqci control/status family

Andes vector dot-product extension

T-Head XTheadFMv floating-point move helper (RV32 high-word transfer)

Vector GCM/GHASH support extension

T-Head XTheadBa address-generation / bit-addressing extension

Qualcomm Xqci load/store multiple family

Vector NIST + carry-less multiply (Zvkn + Zvbc)

Qualcomm comparison / conditional extension family

Vector ShangMi crypto suite (Zvksed + Zvksh + Zvkb + Zvkt)

NIST scalar crypto suite (Zbkb + Zbkc + Zbkx + Zkne + Zknd + Zknh)

T-Head XTheadCmo cache-management-operations extension

XMAC → NEORV32 CFU port evidence: generated VHDL adapter + differential test report.

Qualcomm Xqci I/O instruction family

T-Head XTheadInt fast interrupt prologue/epilogue extension

Qualcomm Xqci load-immediate arithmetic family

T-Head XTheadMac multiply-accumulate DSP extension

T-Head XTheadMemIdx indexed and post/pre-increment memory operations

T-Head XTheadBs bit-set / bit-select extension

SiFive L1 data cache discard extension

Andes BF16 conversion extension

Andes vector small-integer load extension

T-Head XTheadMemPair paired-register load/store memory operations

Snitch floating-point repetition extension

Snitch DMA / custom memory-movement extension

SiFive FP/vector exponent helper family, 16-bit variant

Qualcomm Xqci load-immediate family

SiFive L1 data cache flush extension

Andes performance extension family

Andes vector packed FP16 extension

T-Head XTheadCondMov conditional-move extension

XMAC → CVA6 CV-X-IF port evidence: generated Verilog MVP adapter + differential test report.

Snitch Stream Semantic Registers extension

Vector SM3 instruction extension

Qualcomm Xqci synchronization family

Qualcomm base Xqci custom instruction family

SiFive vector widening MAC family

Andes vector BF16 conversion extension

Ventana XVentanaCondOps conditional operations / conditional move extension

Qualcomm Xqci bit-manipulation instruction family

SCARV XCrypto side-channel-resistant cryptography ISA extension

CORE-V XPulp post-increment / register-register memory extension

RISC-V Vector Matrix Extension (working draft, placeholder)

T-Head XTheadSync multi-core synchronization extension

Qualcomm Xqci loop-buffer family

XuanTie Matrix Extension for AI/tile workloads (167 instructions on CUSTOM-1 opcode)

Vector SM4 instruction extension

CHERIoT capability ISA subset on RISC-V (Microsoft / CHERI Alliance)

Vector AES encryption / decryption extension

Rivos XRivosVisni vector integer small new instructions (zero/insert/extract)

Qualcomm Xqci CSR-related family

T-Head XTheadVector RVV-0.7.1 alias extension (XuanTie C906V/C920/R920)

Rivos XRivosVizip vector register zip / unzip operations

T-Head XTheadVdot vector dot-product (4x8-bit MAC into 32-bit elements)

Qualcomm Xqci shift/load/store family

Qualcomm Xqci arithmetic extension family

T-Head XTheadBb bit-manipulation extension

SiFive FP/vector exponent helper family, 32-bit variant

CORE-V XPulp packed-SIMD extension

CORE-V XPulp bit-manipulation extension

CORE-V XPulp event-load extension

SpacemiT Integrated Matrix Extension

CORE-V XPulp multiply-accumulate DSP extension

XMAC → Rocket RoCC port evidence: generated Verilog MVP adapter + differential test report.

Stream Computing matrix extension proposal

CORE-V XPulp general ALU extension

Vector SHA-256 instruction extension

Gemmini custom RoCC ISA for matrix/DNN accelerator operations (UC Berkeley BAR)

RISC-V Packed SIMD / DSP Extension (working draft)

CORE-V XPulp hardware loop extension

CORE-V XPulp branch-immediate extension