@extensilica

Mojo-V privacy-oriented secret computation extension (UMich research)

Basic bit-manipulation crypto helper extension

SHA-256 / SHA-512 hash instruction subset

T-Head XTheadFMemIdx floating-point indexed memory operations

XMAC → PicoRV32 PCPI port evidence: generated Verilog adapter + differential test report.

Vector crypto bit-manipulation extension

Crossbar / permutation helper extension for crypto

SM3 hash instruction subset

AES decryption instruction subset

Entropy source / crypto CSR support

Archived ExtenSilica portability experiment preserved for historical reference. It is not part of the public extension catalog.

AES encryption instruction subset

SiFive vector quantized MAC quad/quad family

SiFive cease / stop instruction extension

Qualcomm Xqci arithmetic/control extension family

SM4 block cipher instruction subset

T-Head XTheadFMv floating-point move helper (RV32 high-word transfer)

SiFive vector quantized MAC dot/odd family

T-Head XTheadCmo cache-management-operations extension

Carry-less multiply extension for cryptographic workloads

Qualcomm Xqci interrupt/integer family

Data-independent execution latency subset

Vector carry-less multiply extension

XMAC → NEORV32 CFU port evidence: generated VHDL adapter + differential test report.

T-Head XTheadBa address-generation / bit-addressing extension

T-Head XTheadSync multi-core synchronization extension

Vector ShangMi + GCM (Zvks + Zvkg)

T-Head XTheadCondMov conditional-move extension

T-Head XTheadMemIdx indexed and post/pre-increment memory operations

SiFive VCIX coprocessor opcode / intrinsic family

XuanTie Matrix Extension for AI/tile workloads (167 instructions on CUSTOM-1 opcode)

CORE-V XPulp post-increment / register-register memory extension

XMAC → CVA6 CV-X-IF port evidence: generated Verilog MVP adapter + differential test report.

SiFive vector fixed-point narrowing / clipping family

T-Head XTheadMac multiply-accumulate DSP extension

Qualcomm Xqci bit/integer instruction family

T-Head XTheadBs bit-set / bit-select extension

Andes vector dot-product extension

T-Head XTheadInt fast interrupt prologue/epilogue extension

CHERIoT capability ISA subset on RISC-V (Microsoft / CHERI Alliance)

Snitch DMA / custom memory-movement extension

Qualcomm Xqci load/store multiple family

Vector AES encryption / decryption extension

Qualcomm Xqci loop/control family

Snitch floating-point repetition extension

T-Head XTheadVector RVV-0.7.1 alias extension (XuanTie C906V/C920/R920)

T-Head XTheadVdot vector dot-product (4x8-bit MAC into 32-bit elements)

Vector GCM/GHASH support extension

Qualcomm Xqci compressed / memory family

Qualcomm Xqci I/O instruction family

SCARV XCrypto side-channel-resistant cryptography ISA extension

Rivos XRivosVizip vector register zip / unzip operations

Qualcomm comparison / conditional extension family

Snitch Stream Semantic Registers extension

SiFive matrix / memory-related vendor family

Qualcomm Xqci compressed / load-immediate style family

T-Head XTheadBb bit-manipulation extension

T-Head XTheadMemPair paired-register load/store memory operations

Qualcomm Xqci control/status family

Vector crypto timing / data-independent execution subset

Ventana XVentanaCondOps conditional operations / conditional move extension

SiFive FP/vector exponent helper family, 32-bit variant

Qualcomm Xqci loop-buffer family

CORE-V XPulp branch-immediate extension

CORE-V XPulp general ALU extension

Vector SHA-256 instruction extension

Qualcomm Xqci load-immediate family

CORE-V XPulp packed-SIMD extension

Andes vector small-integer load extension

SiFive L1 data cache flush extension

Vector crypto bit-manipulation subset (subset of Zvbb)

Andes performance extension family

Andes vector packed FP16 extension

Qualcomm base Xqci custom instruction family

Vector SHA-256 + SHA-512 instruction extension

Vector SM3 instruction extension

Standard scalar crypto umbrella (Zkn + Zkr + Zkt)

Qualcomm Xqci synchronization family

XMAC → Rocket RoCC port evidence: generated Verilog MVP adapter + differential test report.

SiFive vector widening MAC family

Andes vector BF16 conversion extension

CORE-V XPulp multiply-accumulate DSP extension

CORE-V XPulp bit-manipulation extension

Vector NIST crypto suite (Zvkned + Zvknhb + Zvkb + Zvkt)

SiFive FP/vector exponent helper family, 16-bit variant

SiFive L1 data cache discard extension

Vector ShangMi + carry-less multiply (Zvks + Zvbc)

ShangMi scalar crypto suite (Zbkb + Zbkc + Zbkx + Zksed + Zksh)

Qualcomm Xqci bit-manipulation instruction family

RISC-V Vector Matrix Extension (working draft, placeholder)

CORE-V XPulp event-load extension

Qualcomm Xqci CSR-related family

Vector SM4 instruction extension

Rivos XRivosVisni vector integer small new instructions (zero/insert/extract)

SpacemiT Integrated Matrix Extension

Andes BF16 conversion extension

CORE-V XPulp hardware loop extension

Qualcomm Xqci load-immediate arithmetic family

Vector NIST + carry-less multiply (Zvkn + Zvbc)

Qualcomm Xqci shift/load/store family

Qualcomm Xqci arithmetic extension family

Gemmini custom RoCC ISA for matrix/DNN accelerator operations (UC Berkeley BAR)

RISC-V Packed SIMD / DSP Extension (working draft)

NIST scalar crypto suite (Zbkb + Zbkc + Zbkx + Zkne + Zknd + Zknh)

Vector ShangMi crypto suite (Zvksed + Zvksh + Zvkb + Zvkt)

Vector NIST + GCM (Zvkn + Zvkg)

Stream Computing matrix extension proposal