riscv-zvknha

1.0.0Readiness: RL1 — Packaged

by extensilica

Vector SHA-256 instruction extension

Conflicts with 7 extension(s)

Show encoding conflict details

riscv-zvbb INFO

SHARED_MAJOR_OPCODE: opcode 0x57 — shared major opcode; not a conflict by itself. A true conflict requires overlapping full decode mask/match patterns, including any fixed register/immediate field constraints.

riscv-zvbc INFO

SHARED_MAJOR_OPCODE: opcode 0x57 — shared major opcode; not a conflict by itself. A true conflict requires overlapping full decode mask/match patterns, including any fixed register/immediate field constraints.

riscv-zvkg INFO

SHARED_MAJOR_OPCODE: opcode 0x57 — shared major opcode; not a conflict by itself. A true conflict requires overlapping full decode mask/match patterns, including any fixed register/immediate field constraints.

riscv-zvkned INFO

SHARED_MAJOR_OPCODE: opcode 0x57 — shared major opcode; not a conflict by itself. A true conflict requires overlapping full decode mask/match patterns, including any fixed register/immediate field constraints.

riscv-zvknhb WARNING

OPCODE_SHARED: vsha2ms.vv — same instruction in both extensions by spec (encoding details not yet imported)

riscv-zvksed INFO

SHARED_MAJOR_OPCODE: opcode 0x57 — shared major opcode; not a conflict by itself. A true conflict requires overlapping full decode mask/match patterns, including any fixed register/immediate field constraints.

riscv-zvksh INFO

SHARED_MAJOR_OPCODE: opcode 0x57 — shared major opcode; not a conflict by itself. A true conflict requires overlapping full decode mask/match patterns, including any fixed register/immediate field constraints.

Pre-silicon bridge: this package is meant to be evaluable before RTL/FPGA/ASIC decisions.

Install

xsil install riscv-zvknha

Run

xsil run riscv-zvknha

Requires ISA RV64GV_ZVKNHA

Details

Published

May 13, 2026

Latest

1.0.0

Standard

Ratified

RISC-V International

Provenance

Seeded · unverified

Auto-published from upstream by the ExtenSilica catalog-seed agent. The original maintainer has not (yet) claimed authorship.

ISA

RV64GV_ZVKNHA

Readiness

Readiness: RL1 — Packaged

ISAToolchain: externalSim: SpikeTestsRepro: host-dependent

Toolchain

riscv64-unknown-elf · v14.2.0 (external)

Targets

spike

{
  "spike": {
    "config": "sim/spike.yaml",
    "isa": "rv64gv_zvknha",
    "mem": "256m",
    "priv": "msu",
    "status": "skeleton"
  }
}

Cite

CFF and BibTeX for papers and Zenodo (v1.0.0).

CFF

cff-version: 1.2.0
type: software
title: riscv-zvknha
version: 1.0.0
authors:
  - name: extensilica
abstract: Vector SHA-256 instruction extension
message: "If you use this software, please cite it using the metadata from this file."
repository-code: https://github.com/riscv/riscv-crypto
url: https://extensilica.com/package/riscv-zvknha
date-released: 2026-05-13
identifiers:
  - type: url
    value: https://extensilica.com/package/riscv-zvknha
  - type: url
    value: https://github.com/riscv/riscv-crypto

BibTeX

@software{riscv_zvknha_1_0_0,
  title = {riscv-zvknha},
  author = {extensilica},
  year = {2026},
  version = {1.0.0},
  url = {https://extensilica.com/package/riscv-zvknha},
  repository = {https://github.com/riscv/riscv-crypto},
}

Downloads

7 days

30 days

Maintainers

extensilica

Links

Repository

Implementation requests

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Readiness & capabilities

Readiness: RL1 — Packaged

Runnable (entry declared)

Testable (testEntry declared)

Repro: bundled

Repro: resolved

Repro: host-dependent

Toolchain: bundled

Toolchain: external

Sim: Spike

Emu: QEMU

RTL

FPGA

Tests

README

Vector SHA-256 instruction extension

Version History

Version	Published	Size	Downloads	Status
1.0.0latest `xsil install [email protected]`	May 13, 2026	5.8 KB	0	active

Downloads

Last 7 days

Last 30 days

All time

Daily downloads — last 30 days

05-1405-2105-2806-0406-1106-12

By version

1.0.0

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