riscv-zvbc

1.0.0.xsil package

by extensilica

Vector carry-less multiply extension

No confirmed encoding conflictsShares encoding space with 7 extension(s)

Show encoding relation details

riscv-zvbb INFO

SHARED_MAJOR_OPCODE: opcode 0x57 — shared major opcode; not a conflict by itself. A true conflict requires overlapping full decode mask/match patterns, including any fixed register/immediate field constraints.

riscv-zvkg INFO

SHARED_MAJOR_OPCODE: opcode 0x57 — shared major opcode; not a conflict by itself. A true conflict requires overlapping full decode mask/match patterns, including any fixed register/immediate field constraints.

riscv-zvkned INFO

SHARED_MAJOR_OPCODE: opcode 0x57 — shared major opcode; not a conflict by itself. A true conflict requires overlapping full decode mask/match patterns, including any fixed register/immediate field constraints.

riscv-zvknha INFO

SHARED_MAJOR_OPCODE: opcode 0x57 — shared major opcode; not a conflict by itself. A true conflict requires overlapping full decode mask/match patterns, including any fixed register/immediate field constraints.

riscv-zvknhb INFO

SHARED_MAJOR_OPCODE: opcode 0x57 — shared major opcode; not a conflict by itself. A true conflict requires overlapping full decode mask/match patterns, including any fixed register/immediate field constraints.

riscv-zvksed INFO

SHARED_MAJOR_OPCODE: opcode 0x57 — shared major opcode; not a conflict by itself. A true conflict requires overlapping full decode mask/match patterns, including any fixed register/immediate field constraints.

riscv-zvksh INFO

SHARED_MAJOR_OPCODE: opcode 0x57 — shared major opcode; not a conflict by itself. A true conflict requires overlapping full decode mask/match patterns, including any fixed register/immediate field constraints.

This versioned archive records the Extension's encoding, dependencies, provenance, documentation, and any simulator, toolchain, RTL, test, or hardware support declared by its maintainer.

Install package

xsil install riscv-zvbc

Details

Published

May 12, 2026

Latest

1.0.0

Standard

Ratified

RISC-V International

Provenance

Seeded · unverified

Auto-published from upstream by the ExtenSilica catalog-seed agent. The original maintainer has not (yet) claimed authorship.

ISA

RV64GV_ZVBC

License

CC-BY-4.0

Cite

CFF and BibTeX for papers and Zenodo (v1.0.0).

CFF

cff-version: 1.2.0
type: software
title: riscv-zvbc
version: 1.0.0
authors:
  - name: extensilica
abstract: Vector carry-less multiply extension
message: "If you use this software, please cite it using the metadata from this file."
license: CC-BY-4.0
repository-code: https://github.com/riscv/riscv-crypto
url: https://extensilica.com/package/riscv-zvbc
date-released: 2026-05-12
identifiers:
  - type: url
    value: https://extensilica.com/package/riscv-zvbc
  - type: url
    value: https://github.com/riscv/riscv-crypto

BibTeX

@software{riscv_zvbc_1_0_0,
  title = {riscv-zvbc},
  author = {extensilica},
  year = {2026},
  version = {1.0.0},
  url = {https://extensilica.com/package/riscv-zvbc},
  license = {CC-BY-4.0},
  repository = {https://github.com/riscv/riscv-crypto},
}

Downloads

7 days

30 days

Maintainers

extensilica

Links

Repository

Package metadata

Metadata is published by the package maintainer. Inspect the archive, upstream sources, and checksums before depending on declared support.

Required ISA: RV64GV_ZVBC
Declared support: spike
Toolchain: riscv64-unknown-elf · v14.2.0 (external)
Capabilities: ISAToolchain: externalSim: SpikeTestsRepro: host-dependententrytestEntry
Resolution: host-dependent
Archive checksum: sha256:8ca691d81aa99a57f40fca3454bcba45d4940d1c28f38ecc2ac5b1160f66cd04
Payload checksum: sha256:77a95515773af04822173983f902226de9b6f597a9dc148cc20c28bd78b3a5d8

Support metadata

{
  "spike": {
    "config": "sim/spike.yaml",
    "isa": "rv64gv_zvbc",
    "mem": "256m",
    "priv": "msu",
    "status": "skeleton"
  }
}

Dependencies

{
  "tools": []
}

README

Vector carry-less multiply extension

Version History

Version	Published	Size	Downloads	Status
1.0.0latest Initial catalog-seed scaffold for riscv-zvbc (2 base mnemonics, 4 encodings; SEW=64 only), derived from upstream 9cb9087. `xsil install [email protected]`	May 12, 2026	6.6 KB	3	active

Downloads

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Daily downloads — last 30 days

07-1307-2007-2708-0308-1008-11

By version

1.0.0

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